User contributions for 2A00:23C6:D503:D801:D91:6395:7B61:9865
For 2A00:23C6:D503:D801:D91:6395:7B61:9865 talk block log logs filter log
15 May 2024
- 18:3018:30, 15 May 2024 diff hist −5 Tegra Drake's memclock (and by extension its bandwidth already in the table) is LPDDR5X-class. Given it sems to be an ASIC, LPDDR5 shouldn't be included unless there is evidence Drake can be or has been configured with it. Tag: Visual edit
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