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Pentium: Revision history

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For any version listed below, click on its date to view it. For more help, see Help:Page history and Help:Edit summary. (cur) = difference from current version, (prev) = difference from preceding version, m = minor edit, → = section edit, ← = automatic edit summary

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24 May 2024

19 May 2024

  • curprev 18:4018:40, 19 May 2024‎ 2001:14ba:a846:f000::2000 talk‎ 41,748 bytes +18‎ →‎Pentium M: CPU architecture FSB speed is listed with "MT/s" transfer speed units, the bus is in-fact a hot rodded P6 chip GPTL and it its clock rate is 400-533Mhz, this is can be expressed as 400MT/s as well, but this causes confusion with P4 and Mobile P4 and later CPUs like Core Solo / Duo and Core 2 Solo / Duo which use DDR FSB technology. This is significant because the P6 chip at the time didn't like non-parity clock rates with memory controllers undo Tag: Visual edit

16 May 2024

12 May 2024

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